Documentation AN4011 - Choosing The Right Cypress Synchronous SRAM The purpose of this application note is to provide a means to determine which architecture is right for a particular application. A brief description of each architecture and comparison by address/data relationships and performance characteristics is also included.

The table below shows the architecture comparison for the different options:                                                                            


Std. Sync




Data Rate





Data Bus

Common I/O

Common I/O

Common and Separate I/O

Separate I/O







LVTTL 3.3V/2.5V

LVTTL 3.3V/3.5V

HSTL (1.5V/1.8V)

HSTL (1.5V/1.8V)

Clock Frequency

250 MHz

250 MHz

333 MHz / 550 MHz

333 MHz / 550 MHz
Thu, 25 Jun 2015 06:23:34 -0600
AN58815 - Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs
The 65nm technology QDR family  of  devices  offers significant advantages over the 90nm  technology  family. 

The 65-nm technology QDR family of devices offers significant advantages over the 90-nm technology family. This application note describes these advantages and provides guidelines to migrate from 90-nm to 65-nm devices.
The advantages of the 65nm Technology devices are as follows and is described in detail in this application note:
  • Faster Operating Frequencies
  • Lower Power Consumption
  • Improved Data Valid Window
  • Improved Signal Integrity
  • Lower Input and Output Capacitances
Wed, 06 May 2015 07:50:32 -0600
AN4017 - Understanding Temperature Specifications: An Introduction AN4017 gives a basic understanding of the temperature specifications found in Cypress's product datasheets. There are many factors that affect the thermal operation of a device. This application note also gives you an understanding of the thermal parameters and temperature specifications of the device. 

This document describes the various thermal parameters namely Ambient Temperature (Ta), Case Temperature (Tc), Junction Temperature(Tj), Thermal Resistance, Power Dissipation etc.

Details on calculating Junction Temperature are provided in this application note.

Clicking on the link below provides a tool which enables calculation of the I/O Switching Current (Iddq) for desired frequency, Total Power Consumption and Junction Temperature for Sync SRAMs

Please refer to the respective product datasheets to get the Vdd voltage and Idd current used in the formula.

Wed, 06 May 2015 07:20:02 -0600
AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide Cypress Quad Data RateTM-II (QDRTM-II),QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for communication and data storage applications. The purpose of this application note is to assist designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.


Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

Wed, 06 May 2015 07:14:51 -0600
AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM, and Nonvolatile SRAM (nvSRAM) but does not contain soft error rate (SER) data for any of the SRAMs. Individual datasheets for Synchronous SRAMs list the derived accelerated neutron failure rates. ]]> Thu, 26 Feb 2015 23:28:50 -0600 CY7C1303BV25: 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture


  • Separate independent read and write data ports
  • 167 MHz clock for high bandwidth
  • Two word burst on all accesses
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz
  • Two input clocks (K and K) for precise DDR timing
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • For more, see pdf

Functional Description
The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM equipped with QDR® architecture. QDR architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Wed, 24 Dec 2014 01:32:33 -0600
Termination of Input Pins in Sync SRAMs – KBA82779 Answer: Pull-up resistor termination is recommended for all input pins. However, termination may not be required for control signals if the signal integrity looks good from SI simulations and the frequency of operation is less than 200 MHz.

Some Sync SRAMs belonging to QDR II+ and DDR II+ have on-die termination (ODT) on data input signals, control signals (byte write select signals), and input clocks (K and /K clocks). For such SRAMs, external termination resistors are not required.

QDR IV parts have programmable ODT for clock, address/command, and data inputs. Therefore, external termination is not required on these inputs.

Fri, 17 Oct 2014 00:59:54 -0600
QTP 051207: 18 MEG QDR SYNCHRONOUS SRAM FAMILY R9Q-3R TECHNOLOGY, FAB4 Fri, 27 Jun 2014 03:00:15 -0600 Routing Clocks in QDR/DDR Sync SRAM – KBA89151 Answer: The clocks in QDR/DDR Sync SRAMs should be routed as single-ended. The echo clocks (CQ and /CQ), which are used to simplify data capture on high-speed systems, are not truly differential signals. They are single-ended signals that are 180 degrees out of phase. So, you need to route these signals as single-ended, but ensure that both signals have minimum skew with respect to each other.

The same is true for the input clocks (K and /K). Please note that there is no differential receiver in the SRAM. The memory uses the rising edges of K and /K to latch input signals. Both clocks are single-ended signals. Although they are not truly differential, it is best to keep K and /K 180 degrees out of phase with respect to one another.

Please note that although there is no special requirement to route CQ and /CQ and K and /K close to each other, the trace characteristic length should match so that there is no skew between them. Since these are pseudo-differential clocks, the rising edge of one clock and the falling edge of the other clock should match.

Fri, 04 Apr 2014 06:42:13 -0600
Nature of Clock Phase Jitter in DDR/QDR™ Sync SRAM – KBA89153 Answer: The QDR Consortium officially specifies input-clock phase jitter as cycle-to-cycle jitter, which measures the change in clock period measurement between any two adjacent clock cycles.

Mathematically, the cycle-to-cycle jitter can be represented as follows:

Tcycle (n) – Tcycle (n+1)
where Tcycle (n) and Tcycle (n+1) are any two adjacent cycles measured on controlled edges.

Consider the following figure, which shows the various cycles of the input clock K:

Suppose the QDR/DDR Sync SRAM is operated at 250 MHz. Then the K clock period ideally should be 4 ns.

  • For zero jitter, Tcycle (n) = Tcycle (n+1) = 4 ns.
  • If Tcycle (n) = 4 ns and Tcycle (n+1) = 3.9 ns, then the jitter would be (4 ns-3.9 ns) = 0.1 ns. This calculated jitter should be less than or equal to the tKC Var parameter specified in the datasheet for proper operation.
Fri, 04 Apr 2014 06:25:34 -0600
K/K# Clocks Routing for QDR<sup>®</sup>II/II+/DDRII/DDRII+ SRAMs – KBA89248 Answer: K/K# clocks should be treated as single-ended signals and have to be routed as independent traces that are decoupled from one another. However, to minimize the timing issues and skew between these clocks at the receiver side, the lengths of these two traces on PCB have to be the same.

The clocks are not true differential signals; they are pseudo-differential clocks. Both clocks are single-ended signals, 180 degrees out of phase with each other. They should be terminated like other signals with pull-up resistor to VTT.

Tue, 18 Mar 2014 01:02:31 -0600
Knowledge Base – Cypress Semiconductor Cage Code – KBA89258 Answer: The Commercial and Government Entity Code, or CAGE Code, is a unique identifier assigned to suppliers to various government or defense agencies, as well as to government agencies themselves and also various organizations.

CAGE codes provide a standardized method of identifying a given facility at a specific location.

Cypress Semiconductor’s Cage Code is 65786.

Cypress Minnesota - Fab4 who ship wafers has Cage Code 5AZZ0.

Ramtron International who specialized memory who and was acquired by Cypress Semiconductor has a CAGE code OJP56.

Fri, 27 Sep 2013 02:08:09 -0600
Separate Supplies for V<sub>TT</sub> and V<sub>REF</sub> – KBA88203 Answer: VTT is the voltage to which the various signals (data, address, control) are externally terminated using a resistor. Typically, VTT is VDDQ/2. VREF, which is the reference input voltage, is also VDDQ/2. However, we do not recommend connecting VTT to VREF.

Instead, we provide a separate power for VTT. If we directly connect VREF to VTT, then any switching noise on the I/Os can be coupled to VREF. As a result, VREF could become unclean, which would create instability.

In addition, VTT has higher current requirements. To calculate the current required for VTT, note that the VTT power is 5/(16R) x VDDQ^2 x (number of inputs terminated to VTT), where R is the external termination resistor. Divide this power by VDDQ to determine the current required for VTT.

The application note cited below shows how to derive the above equation. The derivation is done using an on-die termination (ODT) part, and it shows the ODT power. You would get the same equation by inserting termination outside.

AN42468 − On-Die Termination for QDR™II+/DDRII+ SRAMs

Fri, 13 Sep 2013 04:21:11 -0600
Product Selector Guide (PSG) - All Cypress Products - Japanese Thu, 29 Aug 2013 04:18:19 -0600 Product Selector Guide (PSG) - All Cypress Products Tue, 20 Aug 2013 01:54:18 -0600 Product Selector Guide (PSG) - All Cypress Products - Chinese Mon, 01 Apr 2013 04:35:52 -0600 CY7C1305TV25 - Verilog Fri, 06 Apr 2012 18:03:16 -0600 CY7C1305TV25 - IBIS Fri, 06 Apr 2012 18:02:36 -0600 CY7C1305TV25 - BSDL Fri, 06 Apr 2012 18:01:55 -0600 HSTL compliance of QDR II SRAM Question: In the datasheet of  CY7C1514V18 , it is specified that it has variable drive HSTL output buffers. Will the device operate if High drive strength HSTL-II or HSTL-III are used?

Response:The CY7C1514V18 device uses the HSTL-I class output buffer. It is not completely compliant with HSTL-II. By variable drive HSTL output buffer, we mean that an external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching is between 175 and 350 thus varying output impedance between 35 ohms and 70 ohms. HSTL II compliance depends on what output impedance setting you use for the device (i.e. what resistor value you connect to the ZQ pin). For the nominal 50 Ohms output impedance setting, HSTL Class II is not met. All outputs of QDR-II are 1.5V Class I HSTL compatible

Thu, 13 May 2010 01:44:30 -0600