Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D106 AN58815 - Advantages of 65 nm Technology over 90 nm Technology QDR® Family of SRAMs http://www.cypress.com/?rID=40217
The 65nm technology QDR family  of  devices  offers significant advantages over the 90nm  technology  family. 
This application note describes these  advantages and provides guidelines to migrate from 90nm to 65nm devices. 
 
The advantages of the 65nm Technology devices are as follows and is described in detail in this application note:
 
  • Faster Operating Frequencies
  • Lower Power Consumption
  • Improved Data Valid Window
  • Improved Signal Integrity
  • Lower Input and Output Capacitances
 
]]> Thu, 17 Jan 2013 05:25:09 -0600 AN4011 - Choosing The Right Cypress Synchronous SRAM http://www.cypress.com/?rID=13042 Cypress currently manufactures several major synchronous SRAM architectures. The purpose of this application note is to provide a means to determine which architecture is right for a particular application. In so doing, a brief description will be supplied concerning each architecture and each will be contrasted by address/data relationships and significant performance characteristics. 

The table below shows the architecture comparison for the different options:                                                                            


Parameter
Std. Sync
NoBLTM
DDR-II/DDR-II+
QDRTM-II/ QDRTM-II+

Data Rate
Single
Single
Double
Double

Data Bus
Common I/O
Common I/O
Common and Separate I/O
Separate I/O

VDD
3.3V/2.5V
3.3V/2.5V
1.8V
1.8V

VDDQ
LVTTL 3.3V/2.5V
LVTTL 3.3V/3.5V
HSTL (1.5V/1.8V)
HSTL (1.5V/1.8V)

Clock Frequency
250 MHz
250 MHz
333 MHz / 550 MHz
333 MHz / 550 MHz
]]> Mon, 24 Sep 2012 05:59:52 -0600 AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide http://www.cypress.com/?rID=12889 Cypress Quad Data RateTM-II (QDRTM-II),QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for communication and data storage applications. The purpose of this application note is to assist designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

 

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

]]> Fri, 21 Sep 2012 01:39:56 -0600 AN4017 - Understanding Temperature Specifications: An Introduction http://www.cypress.com/?rID=12896 The following application note is intended to give the reader a basic understanding of the temperature specifications found in Cypress's product datasheets. There are many factors that affect the thermal operation of a device. This application note provides the reader with enough background to understand the thermal parameters and temperature specifications of the device.   

This document describes the various thermal parameters namely Ambient Temperature (Ta), Case Temperature (Tc), Junction Temperature(Tj), Thermal Resistance, Power Dissipation etc.

Details on calculating Junction Temperature are provided in this application note.

Clicking on the link below provides a tool which enables calculation of the I/O Switching Current (Iddq) for desired frequency, Total Power Consumption and Junction Temperature for Sync SRAMs

http://www.cypress.com/?docID=23984

Please refer to the respective product datasheets to get the Vdd voltage and Idd current used in the formula.

]]> Wed, 08 Aug 2012 23:16:56 -0600 CY7C1303BV25: 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture http://www.cypress.com/?rID=38824 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture

Features

  • Separate independent read and write data ports
  • 167 MHz clock for high bandwidth
  • Two word burst on all accesses
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz
  • Two input clocks (K and K) for precise DDR timing
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • For more, see pdf


Functional Description
The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM equipped with QDR® architecture. QDR architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
 

]]> Tue, 31 Jul 2012 01:20:36 -0600 CY7C1305TV25 - Verilog http://www.cypress.com/?rID=61578 Fri, 06 Apr 2012 18:03:16 -0600 CY7C1305TV25 - IBIS http://www.cypress.com/?rID=61577 Fri, 06 Apr 2012 18:02:36 -0600 CY7C1305TV25 - BSDL http://www.cypress.com/?rID=61576 Fri, 06 Apr 2012 18:01:55 -0600 HSTL compliance of QDR II SRAM http://www.cypress.com/?rID=36691 Question: In the datasheet of  CY7C1514V18 , it is specified that it has variable drive HSTL output buffers. Will the device operate if High drive strength HSTL-II or HSTL-III are used?

Response:The CY7C1514V18 device uses the HSTL-I class output buffer. It is not completely compliant with HSTL-II. By variable drive HSTL output buffer, we mean that an external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching is between 175 and 350 thus varying output impedance between 35 ohms and 70 ohms. HSTL II compliance depends on what output impedance setting you use for the device (i.e. what resistor value you connect to the ZQ pin). For the nominal 50 Ohms output impedance setting, HSTL Class II is not met. All outputs of QDR-II are 1.5V Class I HSTL compatible

]]> Thu, 13 May 2010 01:44:30 -0600 18 Meg QDR Synchronous SRAM Family R9Q-3R Technology, Fab4 http://www.cypress.com/?rID=35827 Fri, 23 May 2008 00:00:00 -0600