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User Module Datasheet: SPI Slave Variable Length Datasheet SPISVL V 1.10 (CY8C21x45, CY8C22x45, CY8C28x45, CY8C28xxx) | Cypress Semiconductor

User Module Datasheet: SPI Slave Variable Length Datasheet SPISVL V 1.10 (CY8C21x45, CY8C22x45, CY8C28x45, CY8C28xxx)

Last Updated: 
Jun 02, 2014
Version: 
1.10

Features and Overview

  • Supports Serial Peripheral Interconnect (SPI) Slave protocol
  • Supports protocol modes 0, 1, 2, and 3
  • Selectable input sources for MOSI, SCLK, and ~SS
  • Selectable output routing for MISO
  • Programmable interrupt on SPI Complete or TX Reg Empty conditions
  • SS may be firmware controlled
  • Selectable Data Length - from 9 to 16 bits
     
The SPISVL User Module is a SPIS that can be configured as variable data length. It performs full duplex synchronous data transfers with arbitrary data length between 9 and 16 bits. SCLK phase, SCLK polarity, and LSB First can be specified to accommodate most SPI protocols. The SPISVL PSoC blocks have selectable routing for the input and output signals, and programmable interrupt driven control. Application Programming Interface (API) firmware provides a high level programming interface for either assembly or C application software.
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