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User Module Datasheet: SPI Master Variable Length Datasheet SPIMVL V 1.10 (CY8C21x45, CY8C22x45, CY8C28x45, CY8C28xxx) | Cypress Semiconductor

User Module Datasheet: SPI Master Variable Length Datasheet SPIMVL V 1.10 (CY8C21x45, CY8C22x45, CY8C28x45, CY8C28xxx)

Last Updated: 
Jun 02, 2014
Version: 
1.10

Features and Overview

  • Supports Serial Peripheral Interconnect (SPI) Master protocol
  • Supports SPI clocking modes 0, 1, 2, and 3
  • Selectable input sources for clock and MISO
  • Selectable output routing for MOSI and SCLK
  • Programmable interrupt on SPI Complete or TX Reg Empty conditions
  • SPI Slave devices can be independently selected
  • Selectable Data Length – from 9 to 16 bits
     
The SPI Master Variable Length User Module (SPIMVL) is a Serial Peripheral Interconnect Master that can be configured with a variable data length. It performs full duplex synchronous data transfers with arbitrary data length between 9 and 16 bits. SCLK phase, SCLK polarity, and LSB First can be specified to accommodate most SPI clocking modes. Controlled by user-supplied software, the slave select signal can be configured to control one or more SPI Slave devices. The SPIMVL PSoC blocks have selectable routing for the input and output signals, and programmable interrupt-driven control.