You are here

User Module Datasheet: SPI MASTER DATASHEET, SPIM V 2.6 (CY8C29/27/24/22/21xxx, CY7C603xx, CY7C64215, CYWUSB6953, CY8C23x33, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST110, CY8CTMG110, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8CTMA140, CY8C21x45... | Cypress Semiconductor

User Module Datasheet: SPI MASTER DATASHEET, SPIM V 2.6 (CY8C29/27/24/22/21xxx, CY7C603xx, CY7C64215, CYWUSB6953, CY8C23x33, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST110, CY8CTMG110, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8CTMA140, CY8C21x45...

Last Updated: 
May 22, 2014
Version: 
2.6

Features and Overview

  • Supports Serial Peripheral Interconnect (SPI) Master protocol
  • Supports SPI clocking modes 0, 1, 2, and 3
  • Selectable input sources for clock and MISO
  • Selectable output routing for MOSI and SCLK
  • Programmable interrupt on SPI-done condition
  • SPI Slave devices can be independently selected

The SPIM User Module is a Serial Peripheral Interconnect Master. It performs full duplex synchronous 8-bit data transfers. SCLK phase, SCLK polarity, and LSB First can be specified to accommodate most SPI clocking modes. Controlled by user-supplied software, the slave select signal can be configured to control one or more SPI Slave devices. The SPIM PSoC block has selectable routing for the input and output signals, and programmable interrupt-driven control.
Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.