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User Module Datasheet: Shadow Registers Datasheet ShadowRegs V 1.1 (CY8C20x34/36, CY8C21x12, CY8C29/27/24/22/21xxx, CY8C20336AN/436AN/636AN, CY8C20xx6AS, CY8C20XX6L, CY8C20x46/96, CY8C20045/55, CY7C64215/343, CY7C60413, CY7C603xx, CY8CLED02/04/08/16,... | Cypress Semiconductor

User Module Datasheet: Shadow Registers Datasheet ShadowRegs V 1.1 (CY8C20x34/36, CY8C21x12, CY8C29/27/24/22/21xxx, CY8C20336AN/436AN/636AN, CY8C20xx6AS, CY8C20XX6L, CY8C20x46/96, CY8C20045/55, CY7C64215/343, CY7C60413, CY7C603xx, CY8CLED02/04/08/16,...

Last Updated: 
Oct 23, 2012
Version: 
1.1

Features and Overview

  • Provides a global shadow register for a selected port data register
  • Generates a set of macros for port pin manipulation
  • Prevents corruption of GPIO pin settings during CPU control of GPIO
  • Cooperates with other user modules that allocate shadow registers.
     
The ShadowRegs user module creates a RAM variable (the shadow register) that caches values written to a port data register (PRTxDR). Using a shadow register enables CPU control of an individual GPIO output pin without the risk of corrupting the settings of other GPIO pins sharing the same port.