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User Module Datasheet: I2C Hardware Block Datasheet, I2CSBUF V 1.00 (CY8C20xx7/S, CY8C20055, CY8C24093, CY8C24393, CY8C24293, CY8C24693) | Cypress Semiconductor

User Module Datasheet: I2C Hardware Block Datasheet, I2CSBUF V 1.00 (CY8C20xx7/S, CY8C20055, CY8C24093, CY8C24393, CY8C24293, CY8C24693)

Last Updated: 
Dec 17, 2014
Version: 
1.00
Features and Overview
  • Industry standard Philips I2C bus compatible interface
  • Slave-only operation
  • Only two pins (SDA and SCL) are required to interface to I2C bus
  • Standard data rate of 50, 100, and 400 kbps
  • No clock stretching
  • 32-byte hardware data buffer

The I2CSBUF User Module implements an I2C register based slave device. The I2C bus is an industry standard, two wire hardware interface developed by Philips® (now NXP). The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CSBUF user module supports the standard mode with speeds of as much as 400 kbps. The I2CSBUF user module is compatible with multiple devices on the same bus.

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