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User Module Datasheet: I2C Hardware Block Datasheet I2CHW V 2.00 | Cypress Semiconductor

User Module Datasheet: I2C Hardware Block Datasheet I2CHW V 2.00

Last Updated: 
Sep 02, 2016
Version: 
*M

Features and Overview

  • Industry standard Philips I2C bus compatible interface
  • Master and Slave operation, Multi Master capable
  • Only two pins (SDA and SCL) required to interface to I2C bus
  • Standard data rate of 100/400 kbps, also supports 50 kbps
  • High level API requires minimal user programming
  • 7-bit addressing mode

The I2C Hardware User Module implements an I2C device in firmware. The I2C bus is an industry standard, two-wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CHW User Module supports the standard mode with speeds up to 400 kbps. No digital or analog user blocks are consumed with this module. The I2CHW User Module is compatible with other slave devices on the same bus.

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