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User Module Datasheet: DUAL INPUT 7- TO 13-BIT INCREMENTAL ADC DATASHEET, DUALADC V2.30 (CY8C29/27/24XXX, CY8CLED04/08/16, CY8CLED0XD, CY8CLED0XG, CY8C28X45, CY8CPLC20, CY8CLED16P01, CY8C28X43, CY8C28X52) | Cypress Semiconductor

User Module Datasheet: DUAL INPUT 7- TO 13-BIT INCREMENTAL ADC DATASHEET, DUALADC V2.30 (CY8C29/27/24XXX, CY8CLED04/08/16, CY8CLED0XD, CY8CLED0XG, CY8C28X45, CY8CPLC20, CY8CLED16P01, CY8C28X43, CY8C28X52)

Last Updated: 
Jun 14, 2013
Version: 
2.30

Features and Overview
 

  • Samples two inputs simultaneously
  • 7- to 13-bit resolution
  • 2’s complement or unsigned integer
  • Sample rates from 4 to greater than 10,000 sps
  • Multiple input ranges including Vss to Vdd
  • Integrating Converter provides good normal mode rejection
  • Internal or external clock
     

The DualADC User Module is a dual input incremental ADC with an adjustable resolution between 7 and 13 bits. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output can be configured as 2’s complement or unsigned integer. The DualADC is ideal for applications that require simultaneous sampling of two signals, such as power measurement. As with other PSoC ADCs, signals to both inputs may be multiplexed. The CPU load varies with the input level. For example, when Vin = Vref, there are 10,014 CPU cycles (maximum 13 bit). When Vin = AGND, there are 5,278 CPU cycles (average 13 bit). When Vin = -Vref, there are 542 CPU cycles (minimum 7-13 bit).

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