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User Module Datasheet: Delta Sigma ADC Datasheet DelSigPlus V 1.10 (CYC8C24x94, CY8CLED0xD, CY8CLED0xG, CY8C28x45, CY8C28x43) | Cypress Semiconductor

User Module Datasheet: Delta Sigma ADC Datasheet DelSigPlus V 1.10 (CYC8C24x94, CY8CLED0xD, CY8CLED0xG, CY8C28x45, CY8C28x43)

Last Updated: 
Jun 10, 2013
Version: 
1.10

Features and Overview

  • 6-bit to 14-bit resolution
  • Data in unsigned or signed 2’s complement formats
  • Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
  • Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
  • First Order or Second Order modulator for improved signal-to-noise ratio, user selectable
  • Input range defined by internal and external reference options
  • Requires no digital blocks

The DelSigPlus User Module is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs invalidates the first two samples following the change. Refer to the Parameters section prior to module placement.

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