You are here

User Module Datasheet: 7- to 13-Bit Variable Resolution Incremental ADC Datasheet ADCINCVR V 4.00 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x... | Cypress Semiconductor

User Module Datasheet: 7- to 13-Bit Variable Resolution Incremental ADC Datasheet ADCINCVR V 4.00 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x...

Last Updated: 
Aug 20, 2015
Version: 
4.00

Features and Overview

  • 7- to 13-bit resolution, 2’s complement
  • Sample rate from 4 to 5018 sps
  • Input range Vss to Vdd
  • Integrating converter provides good normal-mode rejection
  • Internal or external clock
     

The ADCINCVR is an integrating ADC with an adjustable resolution between 7 and 13 bits. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output is 2’s complement based on an input voltage between –Vref and Vref centered at AGND.

Sample rates from 4 to 5018 sps are achievable depending on the selection of the resolution, DataClock, and CalcTime parameters.

The programming interface allows you to specify the number of sequential samples to be taken or to select continuous sampling. The CPU load varies with the input level. For example, when Vin = Vref, there are 5076 CPU cycles (maximum 13 bit). When Vin = AGND, there are 2708 CPU cycles (average 13 bit). When Vin = -Vref, there are 340 CPU cycles (minimum 7-13 bit).

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.