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User Module Datasheet: 6 to 14-Bit Delta Sigma ADC Datasheet DelSigMulti V 1.30 (CY8C28X45, CY8C28X43, CY8C28X52, CY8C28X33, CY8C28X23) | Cypress Semiconductor

User Module Datasheet: 6 to 14-Bit Delta Sigma ADC Datasheet DelSigMulti V 1.30 (CY8C28X45, CY8C28X43, CY8C28X52, CY8C28X33, CY8C28X23)

Last Updated: 
Dec 17, 2014
Version: 
1.30

Features and Overview

  • 6-bit to 14-bit resolution
  • Two to Four channels of synchronized sampling
  • Data in unsigned or signed 2’s complement formats
  • Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
  • Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
  • First Order or Second Order modulator for improved signal-to-noise ratio, user selectable
  • Input range defined by internal and external reference options
  • Requires no digital blocks
  • Configuration wizard enables you to easily select between two, three, or four channels of delta-sigma ADC measurements that are all synchronized with each other
  • The internal timer of the decimators allows no digital block use
     

The DelSigMulti User Module is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs invalidates the first two samples after the change. This DelSigMulti User Module supports up to four channels of simultaneous, synchronized deltasigma ADC sampling.

A configuration wizard allows you to easily select the number of analog blocks that are used by each channel and the decimator oversample rate of each channel.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.