User Module Datasheet: 11-Bit Delta Sigma ADC Datasheet DELSIG11 V 3.2 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16, CY8C28x45) | Cypress Semiconductor
User Module Datasheet: 11-Bit Delta Sigma ADC Datasheet DELSIG11 V 3.2 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16, CY8C28x45)
Features and Overview
Data format available in 2’s complement
Sample rate to 7.8 ksps
256X over sampling with sinc2 filter reduces antialias requirements
Input range defined by internal and external reference options
Internal or external clock
Note: If this user module is used with the CY8C29xxx family, it consumes an extra 6 mA. As an alternate, use the Delsig user module instead.
The DELSIG11 User Module provides an 11-bit output. It is based on a 2.6V full scale input range centered around a user selected AGND, when the reference selection in the global parameter window is set to +/- Bandgap. The DELSIG11 supports sample rates from 125 sps to 7.8 ksps, and provides a 2’s complement output. The sample rate is determined by the data clock input and is selectable by the user. Data generated by the DELSIG11 is available in the interrupt routine where the data is collected or through polling functions furnished by the DELSIG11 API.
The DELSIG11 is a pipeline integrating converter, requiring 511 integration cycles to generate a single output sample. If this converter is to have a multiplexed input, two samples must pass before the third and following samples are valid. Note that you need to review the Parameters section before module placement.