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Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) Devices | Cypress Semiconductor

Product How-To: Controlling Power in Cypress Programmable SoC (PSoC) Devices

Last Updated: 
Sep 23, 2011

SOCs (System on Chip) are getting complex by the day and IP (Intellectual Property) reuse is an important factor in achieving quick success. Being able to capture most of the design in Soft IPs i.e. IPs not bound to a technology, gives a boost to IP re-use. Until recently, static power consumption was one aspect that was not addressed in soft IPs. With the advent of IEEETM1801 Unified Power Format (UPF), soft-IPs can now have an accompanying power intent file that allows specifying power architecture. With static power being a major concern for shrinking technologies, catching on to UPF would be a step in the right direction. This paper provides insight into UPF and specific examples on how certain low power requirements are accomplished using UPF. It also connects the understanding of high level power requirements to gate level implementation aspects.