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I2C Bus Design and Test for Embedded Systems: Part 2 | Cypress Semiconductor

I2C Bus Design and Test for Embedded Systems: Part 2

Last Updated: 
Sep 23, 2008

Since most microcontroller vendors offer I2C master and slave capabilities on most of their devices, there is nothing to prevent an embedded designer from taking advantage of I2C.

In this part, we will concentrate on strategies for a smooth verification of a custom I2C slave device, taking advantage of the fact that I2C is a low- to medium-data-rate master/slave communication bus.

Remember, the physical layer is a simple handshaking protocol that relies upon open collector outputs on the bus devices and the device driving or releasing the bus lines. The simple hardware design and relatively low data rates allow any engineer to take advantage of I2C as a communication solution. To view more on this topic, click the download link above.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.