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Buffers minimize jitter in clock distribution, differential signal lines | Cypress Semiconductor

Buffers minimize jitter in clock distribution, differential signal lines

Last Updated: 
Nov 13, 2008

EE Times (USA)

http://www.eet.com/story/OEG20021002S0036

High performance clock buffers - those without phase-locked loops (PLLs) - are often used in communications designs for duplication, distribution and fanout of clock signals." Sensitivity to long-term jitter is a critical concern in these applications. Errors resulting from the accumulation of jitter will severely degrade system performance and reliability. While very much less sensitive than a PLL-based buffer, these devices do have a specific contribution of short term jitter - measured as cycle-to-cycle jitter. There is an additional error, with respect to the input reference, from propagation delay and output skew...