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HyperBus™ Master Interface Controller IP (Intellectual Property) Package | Cypress Semiconductor

HyperBus™ Master Interface Controller IP (Intellectual Property) Package

Last Updated: 
Nov 02, 2016

Cypress offers a HyperBus Master Interface Controller IP Package to our qualified customers and partners. The IP Package is a collection of RTL (Register-transfer level) source code and documentation intended to help designers add support for HyperBus to their FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), or ASSP (Application-Specific Standard Product) host controller platform. The Controller IP is offered free of charge and is royalty-free (see "HyperBus Interface Materials End User License Agreement" for full details). The Controller IP supports both HyperFlash™ and HyperRAM™ products.

The HyperBus Master Interface Controller IP Package includes the following software and materials:

  • HyperBus Controller Verilog HDL RTL Source Code
  • HyperBus Controller IP Specification
  • System Verilog Test Bench (AXI4 and AXI3)
  • Verilog Memory Behavioral Model (HyperFlash and HyperRAM)
  • Test Specification
  • Test (Verification Report)
  • Test Script
  • Application Note for AMBA AXI

To request access to the HyperBus Memory Controller IP Package, please complete the form here: http://learn.cypress.com/HyperBusPackage