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PSoC 5LP Device Programming Specification | Cypress Semiconductor

PSoC 5LP Device Programming Specification

Last Updated: 
Apr 28, 2017

PSoC® 5LP device programming refers to the programming of nonvolatile memory in PSoC 5LP using an external host pro-grammer. In the context of external host programmers, nonvolatile memory includes device configuration nonvolatile latch (NVL) flash memory and write once NVL. PSoC 5LP supports programming through the Serial Wire Debug (SWD) interface or Joint Test Action Group (JTAG) interface. The data to be programmed is stored in a hex file. This programming specifica¬tions document explains the hardware connections, programming protocol, programming vectors, and the timing information for developing programming solutions for a PSoC 5LP device