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Silicon Errata Document for RAM9 (90-nm), 72-Mb (CY7C147*/*V25, CY7C148*/*V25), 18-Mb (CY7C137*D/*DV25, CY7C138*D/*DV25) & 4-Mb (CY7C132/3/4/5*G) Synchronous & NoBL™ SRAMs | Cypress Semiconductor

Silicon Errata Document for RAM9 (90-nm), 72-Mb (CY7C147*/*V25, CY7C148*/*V25), 18-Mb (CY7C137*D/*DV25, CY7C138*D/*DV25) & 4-Mb (CY7C132/3/4/5*G) Synchronous & NoBL™ SRAMs

Last Updated: 
Feb 01, 2012
Version: 
*G

This document describes the Ram9 Sync/NOBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.