You are here

S25FL064L, 64-Mbit (8-Mbyte) 3.0 V FL-L SPI Flash Memory | Cypress Semiconductor

S25FL064L, 64-Mbit (8-Mbyte) 3.0 V FL-L SPI Flash Memory

Last Updated: 
May 28, 2017
Version: 
*C

The Cypress FL-L Family devices are Flash Non-volatile Memory products using: - Floating Gate technology - 65-nm process lithography The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO), and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.