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PSoC® 4: PSoC 4XX8_BLE Family Datasheet - Programmable System-on-Chip (PSoC®) | Cypress Semiconductor

PSoC® 4: PSoC 4XX8_BLE Family Datasheet - Programmable System-on-Chip (PSoC®)

Last Updated: 
Jun 21, 2017

General Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4XX8_BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4XX8_BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.


  • 32-bit MCU Subsystem
    • 48-MHz ARM Cortex-M0 CPU with single-cycle multiply
    • Up to 256 KB of flash with Read Accelerator
    • Up to 32 KB of SRAM
  • BLE Radio and Subsystem
    • 2.4-GHz RF transceiver with 50-Ω antenna drive
    • Digital PHY
    • Link Layer engine supporting master and slave modes
    • RF output power: –18 dBm to +3 dBm
    • RX sensitivity: –89 dBm
    • RX current: 16.4 mA
    • TX current: 15.6 mA at 0 dBm
    • Received Signal Strength Indication (RSSI): 1-dB resolution
  • Programmable Analog
    • Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode
    • 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
    • Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
    • Two low-power comparators that operate in Deep-Sleep mode
  • Programmable Digital
    • Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapath
    • Cypress-provided peripheral component library, user-defined state machines, and Verilog input
  • For more, see pdf
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