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CYF2018V, CYF2036V, CYF2072V: 18/36/72-Mbit Programmable Multi-Queue FIFOs | Cypress Semiconductor

CYF2018V, CYF2036V, CYF2072V: 18/36/72-Mbit Programmable Multi-Queue FIFOs

Last Updated: 
Aug 15, 2016

18/36/72-Mbit Programmable Multi-Queue FIFOs


  • Memory organization
    • Industry’s largest first in first out (FIFO) memory densities: 18-Mbit, 36-Mbit and 72-Mbit
    • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
  • Up to 100-MHz clock operation
  • Unidirectional operation
  • Independent read and write ports
    • Supports simultaneous read and write operations
    • Reads and writes operate on independent clocks upto a maximum ratio of two enabling data buffering across clock domains
    • Supports multiple I/O voltage standard: Low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V  voltage standards.
  • For more, see pdf

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. A maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs.