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CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | Cypress Semiconductor

CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Last Updated: 
Jan 08, 2016
Version: 
*L

144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

  • 144-Mbit density (14 M × 36)
  • 550-MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
  • Available in 2.5 clock cycle latency
  • Two input clocks (K and K) for precise DDR timing
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • Data valid pin (QVLD) to indicate valid data on the output
  • On-die termination (ODT) feature
  • For more, see pdf

Functional Description

The CY7C2670KV18 is 1.8-V synchronous pipelined SRAM equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 36-bit words (CY7C2670KV18) that burst sequentially into or out of the device.