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CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT | Cypress Semiconductor

CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

Last Updated: 
Jan 08, 2016
Version: 
*P

144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

Features

  • Separate independent read and write data ports
  • 333-MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • Available in 2.0-clock cycle latency
  • Two input clocks (K and K) for precise DDR timing
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • Data valid pin (QVLD) to indicate valid data on the output
  • On-die termination (ODT) feature
  • For more, see pdf
     

Functional Description

The CY7C2642KV18, and CY7C2644KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.