You are here

CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | Cypress Semiconductor

CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Last Updated: 
Mar 15, 2016
Version: 
*R

72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

  • 72-Mbit density (4M x 18, 2M x 36)
  • 550 MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
  • Available in 2.5 clock cycle latency
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Data valid pi(QVLD) to indicate valid data othe output
  • For more, see pdf
     

Functional Description

The CY7C1568KV18 and CY7C1570KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.