You are here

CY7C15632KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) | Cypress Semiconductor

CY7C15632KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Last Updated: 
Sep 10, 2015
Version: 
*K

72-Mbit QDR® II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Features

  • Separate Independent Read and Write Data Ports
    • Supports concurrent transactions
  • 500 MHz Clock for High Bandwidth
  • Four-word Burst for Reducing Address Bus Frequency
  • Double Data Rate (DDR) Interfaces oboth Read and Write Ports (data transferred at 1000 MHz) at 500 MHz
  • Available in 2.5 Clock Cycle Latency
  • Two Input Clocks (K and K) for precise DDR Timing
    • SRAM uses rising edges only
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
  • For more, see pdf

Functional Description

The CY7C15632KV18 is a 1.8 V Synchronous Pipelined SRAM, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.