You are here

CY7C1525KV18, CY7C1512KV18, CY7C1514KV18: 72-Mbit QDR® II SRAM Two-Word Burst Architecture | Cypress Semiconductor

CY7C1525KV18, CY7C1512KV18, CY7C1514KV18: 72-Mbit QDR® II SRAM Two-Word Burst Architecture

Last Updated: 
Jan 08, 2016
Version: 
*U

72-Mbit QDR® II SRAM Two-Word Burst Architecture

Features

  • Separate Independent Read and Write Data Ports
    • Supports concurrent transactions
  • 350 MHz Clock for High Bandwidth
  • Two-word Burst on all Accesses
  • Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 700 MHz) at 350 MHz
  • Two Input Clocks (K and K) for precise DDR Timing
    • SRAM uses rising edges only
  • Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
  •  Single multiplexed address input bus latches address inputs for both read and write ports
  • bFor more, see pdf

 

Functional Description

 

The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.