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CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM | Cypress Semiconductor

CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM

Last Updated: 
Aug 28, 2015

72-Mbit (2 M × 36) Flow-Through SRAM


  • Supports 133 MHz bus operations
  • 2 M × 36 common I/O
  • 2.5 V core power supply (VDD)
  • 2.5 V I/O supply (VDDQ)
  • Fast clock to output time
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • For more, see pdf

Functional Description

The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).