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CY7C1471V33: 72-Mbit (2 M × 36) Flow-through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1471V33: 72-Mbit (2 M × 36) Flow-through SRAM with NoBL™ Architecture

Last Updated: 
Nov 21, 2016
Version: 
*U

72-Mbit (2 M × 36) Flow-through SRAM with NoBL™ Architecture

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Supports up to 133 MHz bus operations with zero wait states
  • Data is transferred on every clock
  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow through operation
  • Byte Write capability
  • 3.3 V/2.5 V IO supply (VDDQ)
  • Fast clock-to-output times
  • For more, see pdf

Functional Description

The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.