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CY7C1470BV33, CY7C1472BV33, CY7C1474BV33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1470BV33, CY7C1472BV33, CY7C1474BV33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
Aug 24, 2015
Version: 
*M

72 Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 250 MHz bus operations with zero wait states
    • Available speed grades are 250, 200, and 167 MHz
  • Internally self timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • Single 3.3V power supply
  • 3.3V/2.5V I/O power supply
  • Fast clock-to-output time
  • For more, see pdf
     

Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic,respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle.