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CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture

Last Updated: 
Jan 11, 2016
Version: 
*C

36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Supports up to 133-MHz bus operations with zero wait states
  • Pin-compatible and functionally equivalent to ZBT™ devices
  • Internally self timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow through operation
  • Byte Write capability
  • 3.3 V/2.5 V I/O power supply
  • Fast clock-to-output times
  • For more, see pdf
     

Functional Description

The CY7C1463BV33 is a 3.3 V, 2 M × 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1463BV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.