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CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture

Last Updated: 
Jul 28, 2016
Version: 
*O

36 Mbit (1M x 36/2 M x 18) Flow-Through SRAM with NoBL™ Architecture

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Supports up to 133 MHz bus operations with zero wait states
    • Data is transferred on every clock
  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow through operation
  • Byte write capability
  • 3.3V and 2.5V I/O power supply
  • Fast clock-to-output times
    • 6.5 ns (for 133 MHz device)
  • For more, see pdf
     

Functional Description

The CY7C1461AV33/CY7C1463AV33 are 3.3 V, 1 M × 36/2 M × 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle.