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CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) | Cypress Semiconductor

CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Last Updated: 
Aug 05, 2016
Version: 
*K

36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Features

  • Pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT™)
  • Supports 250-MHz bus operations with zero wait states
    • Available speed grades are 250, 200, and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully-registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • 3.3-V power supply
  • 3.3-V/2.5-V I/O power supply
  • Fast clock-to-output time
    • 2.5 ns (for 250-MHz device)
  • Clock enable (CEN) pin to suspend operation
  • Synchronous self-timed writes
  • CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA packages.
  • IEEE 1149.1 JTAG-compatible boundary scan
  • Burst capability—linear or interleaved burst order
  • “ZZ” sleep mode option
  • On Chip Error Correction Code (ECC) to reduce Soft Error Rate (SER)

Functional Description

The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are 3.3 V, 1 M × 36, and 2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

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