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CY7C1444KV33, CY7C1445KV33: 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM | Cypress Semiconductor

CY7C1444KV33, CY7C1445KV33: 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM

Last Updated: 
Aug 04, 2016
Version: 
*G

36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM

Features

  • Supports bus operation up to 250 MHz
  • Available speed grades is 250 MHz
  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double-cycle deselect)
  • Depth expansion without wait state
  • 3.3 V core power supply
  • 2.5 V/3.3 V I/O power supply
  • Fast clock-to-output times
    • 2.5 ns (for 250-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • User-selectable burst counter supporting interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed writes
  • Asynchronous output enable
  • CY7C1444KV33, CY7C1445KV33 available in JEDEC-standard Pb-free 100-pin TQFP packages
  • “ZZ” sleep mode option

Functional Description

The CY7C1444KV33/CY7C1445KV33 SRAMs integrate 1 M × 36/2 M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

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