CY7C1444AV33: 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM | Cypress Semiconductor
CY7C1444AV33: 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM
36-Mbit (1 M × 36) Pipelined DCD Sync SRAM
- Supports bus operation up to 250 MHz
- Available speed grades are 250 MHz and 167 MHz
- Registered inputs and outputs for pipelined operation
- Optimal for performance (double-cycle deselect)
- Depth expansion without wait state
- 3.3 V core power supply
- 2.5 V/3.3 V I/O power supply
- For more, see pdf.
The CY7C1444AV33 SRAM integrates 1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).