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CY7C1441KV33, CY7C1443KV33, CY7C1441KVE33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM (With ECC) | Cypress Semiconductor

CY7C1441KV33, CY7C1443KV33, CY7C1441KVE33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM (With ECC)

Last Updated: 
Aug 04, 2016

36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM (With ECC)


  • 1 M × 36/2 M × 18 common I/O
  • 3.3 V core power supply
  • 2.5 V or 3.3 V I/O power supply
  • Fast clock-to-output times
    • 6.5 ns (133-MHz version)
  • Provide high-performance 2-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed write
  • Asynchronous output enable
  • CY7C1441KV33, CY7C1443KV33 and CY7C1441KVE33 are available in JEDEC-standard Pb-free 100-pin TQFP and Pb-free 165-ball FBGA packages.
  • IEEE 1149.1 JTAG-Compatible Boundary Scan
  • “ZZ” Sleep Mode option
  • Supports 133-MHz bus operations
  • On Chip Error Correction (ECC) to reduce SER

Functional Description

The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are 3.3 V, 1 M × 36/2 M × 18/1 M × 36 synchronous flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock (CLK) input. The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

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