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CY7C1441KV25: 36-Mbit (1 M × 36) Flow-Through SRAM | Cypress Semiconductor

CY7C1441KV25: 36-Mbit (1 M × 36) Flow-Through SRAM

Last Updated: 
Aug 04, 2016

36-Mbit (1 M × 36) Flow-Through SRAM


  • Supports 133 MHz bus operations
  • 1 M × 36 common I/O
  • 2.5 V core power supply
  • 2.5 V I/O power supply
  • Fast clock-to-output times
    • 6.5 ns (133 MHz version)
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self timed write
  • Asynchronous output enable
  • CY7C1441KV25 available in Pb-free 165-ball FBGA package.
  • JTAG boundary scan for FBGA package
  • ZZ sleep mode option

Functional Description

The CY7C1441KV25 is a 2.5 V, 1 M × 36 Synchronous Flow-Through SRAM, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

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