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CY7C1440KV33, CY7C1442KV33, CY7C1440KVE33: 36-Mbit (1 M × 36/2 M × 18) Pipelined Sync SRAM (With ECC) | Cypress Semiconductor

CY7C1440KV33, CY7C1442KV33, CY7C1440KVE33: 36-Mbit (1 M × 36/2 M × 18) Pipelined Sync SRAM (With ECC)

Last Updated: 
Aug 04, 2016
Version: 
*G

36-Mbit (1 M × 36/2 M × 18) Pipelined Sync SRAM (With ECC)

Features

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250 MHz and 167 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply
  • 2.5 V/3.3 V I/O power supply
  • Fast clock-to-output time
    • 2.5 ns (for 250-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • User-selectable burst counter supporting interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed writes
  • Asynchronous output enable
  • Single cycle chip deselect
  • CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are available in Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA packages.
  • IEEE 1149.1 JTAG-compatible boundary scan
  • “ZZ” sleep mode option
  • On-Chip Error Correction (ECC) to reduce SER

Functional Description

The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM integrate 1 M × 36/2 M × 18/1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

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