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CY7C1440KV25: 36-Mbit (1 M × 36) Pipelined Sync SRAM | Cypress Semiconductor

CY7C1440KV25: 36-Mbit (1 M × 36) Pipelined Sync SRAM

Last Updated: 
Aug 04, 2016

36-Mbit (1 M × 36) Pipelined Sync SRAM


  • Supports bus operation up to 250 MHz
  • Available speed grade is 250 MHz
  • Registered inputs and outputs for pipelined operation
  • 2.5 V core power supply
  • 2.5 V I/O power supply
  • Fast clock-to-output times
    • 2.5 ns (for 250-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • User-selectable burst counter supporting interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed writes
  • Asynchronous output enable
  • Single-cycle Chip Deselect
  • CY7C1440KV25 available in Pb-free 165-ball FBGA package.
  • IEEE 1149.1 JTAG-Compatible Boundary Scan
  • “ZZ” Sleep Mode Option

Functional Description

The CY7C1440KV25 SRAM integrates 1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

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