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CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture | Cypress Semiconductor

CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture

Last Updated: 
Dec 20, 2016
Version: 
*N

36-Mbit QDR® II SRAM Two-Word Burst Architecture

Features

  • Separate independent read and write data ports
    • Supports concurrent transactions
  • 333 MHz clock for high bandwidth
  • Two-word burst on all accesses
  • Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • For more, see pdf

Functional Description

The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and  data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.