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CY7C1386KV33/CY7C1387KV33 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM | Cypress Semiconductor

CY7C1386KV33/CY7C1387KV33 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

Last Updated: 
Aug 05, 2016
Version: 
*D

The CY7C1386KV33/CY7C1387KV33 SRAM integrates 512 K × 36/1 M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

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