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CY7C1386D, CY7C1387D: 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM | Cypress Semiconductor

CY7C1386D, CY7C1387D: 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

Last Updated: 
Jul 31, 2016
Version: 
*P

18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM

Features

  • Supports bus operation up to 200 MHz
  • Available speed grades are 200 and 167 MHz
  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double-cycle deselect)
  • Depth expansion without wait state
  • 3.3 V core power supply (VDD)
  • 2.5 V or 3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • For more, see pdf
     

Functional Description

The CY7C1386D/CY7C1387D SRAM integrates 512 K × 36/1 M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).