You are here

CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM | Cypress Semiconductor

CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM

Last Updated: 
Jan 05, 2016
Version: 
*D

18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

Features

  • Supports bus operation up to 200 MHz
  • Available speed grades is 200 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply
  • 2.5 V or 3.3 V I/O power supply
  • Fast clock-to-output times
  • Provides high performance 3-1-1-1 access rate
  • User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed write
  • For more, see pdf

 Functional Description

The CY7C1380DV33/CY7C1382DV33 SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).