You are here

CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33, 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) | Cypress Semiconductor

CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33, 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)

Last Updated: 
Aug 05, 2016
Version: 
*E

The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.