You are here

CY7C1370KV33/CY7C1370KVE33 CY7C1372KV33/CY7C1372KVE33 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) | Cypress Semiconductor

CY7C1370KV33/CY7C1370KVE33 CY7C1372KV33/CY7C1372KVE33 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

Last Updated: 
Jun 28, 2017
Version: 
*H

The CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/CY7C1372KVE33 are 3.3 V, 512 K × 36 and 1 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ logic and ECC functionality.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.