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CY7C1370D, CY7C1372D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1370D, CY7C1372D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
Aug 26, 2015
Version: 
*S

18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 250-MHz bus operations with zero wait states
    • Available speed grades are 250, 200, and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • 3.3 V core power supply (VDD)
  • 3.3 V/2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • For more, see pdf
     

Functional Description

The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and 1 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.