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CY7C1361C, CY7C1363C: 9-Mbit (256 K × 36/512 K × 18) Flow-Through SRAM | Cypress Semiconductor

CY7C1361C, CY7C1363C: 9-Mbit (256 K × 36/512 K × 18) Flow-Through SRAM

Last Updated: 
Nov 21, 2016
Version: 
*S

9-Mbit (256 K × 36/512 K × 18) Flow-Through SRAM

Features

  • Supports 100, 133 MHz bus operations
  • Supports 100 MHz bus operations (Automotive)
  • 256 K × 36/512 K × 18 common I/O
  • 3.3 V – 5% and +10% core power supply (VDD)
  • 2.5 V or 3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 6.5 ns (133-MHz version)
  • Provide high performance 2-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • For more, see pdf
     

Functional Description

The CY7C1361C/CY7C1363C is a 3.3 V, 256 K × 36/512 K × 18 synchronous flow-through SRAMs, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).