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CY7C1360C, CY7C1362C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM | Cypress Semiconductor

CY7C1360C, CY7C1362C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM

Last Updated: 
Nov 20, 2016
Version: 
*R

9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM

Features

  • Supports bus operation up to 200 MHz
  • Available speed grades:  200 and 166 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O operatio(VDDQ)
  • Fast clock-to-output times
    • 3.0 ns (for 200 MHz device)
  • Provide high performance 3-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • For more, see pdf

Functional Description

The CY7C1360C/CY7C1362C SRAM integrates 256 K × 36 and 512 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All  synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3[1]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.