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CY7C1354CV25, CY7C1356CV25: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1354CV25, CY7C1356CV25: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
Nov 21, 2016
Version: 
*Q

9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible with and functionally equivalent to ZBT™
  • Supports 250-MHz bus operations with zero wait states
  • Available speed grades are 250, 200, and 166 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • Single 2.5 V power supply (VDD)
  • Fast clock-to-output times
    • 2.8 ns (for 250-MHz device)
  • For more, see pdf

Functional Description

The CY7C1354CV25/CY7C1356CV25 are 2.5 V, 256 K × 36/512 K × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354CV25/CY7C1356CV25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.