CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor
CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture
Last Updated:
Jan 29, 2018
Version:
*Q
4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
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Supports up to 100-MHz bus operations with zero wait states
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Data is transferred on every clock
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Pin compatible and functionally equivalent to ZBT™ devices
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Internally self timed output buffer control to eliminate the need to use OE
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Registered inputs for flow-through operation
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Byte write capability
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256 K × 18 common I/O architecture
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2.5 V / 3.3 V I/O power supply (VDDQ)
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Fast clock-to-output times
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For more, see pdf
Functional Description
The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.