CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture

4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture

Features

• Supports up to 100-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 256 K × 18 common I/O architecture
• 2.5 V / 3.3 V I/O power supply (V_DDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.