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CY7C13451G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM | Cypress Semiconductor

CY7C13451G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM

Last Updated: 
Jul 17, 2016

4-Mbit (128 K × 36) Flow-Through Sync SRAM


  • 128 K × 36 common I/O
  • 3.3 V core Power Supply (VDD)
  • 2.5 V or 3.3 V I/O Supply (VDDQ)
  • Fast Clock-to-output times
    • 8.0 ns (100 MHz version)
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel Pentium interleaved or Linear Burst Sequences
  • Separate Processor and Controller Address Strobes
  • Synchronous Self Timed Write
  • Asynchronous output enable
  • Available in Pb-free 165-ball FBGA Package
  • ZZ Sleep Mode option
  • For more, see pdf.

Functional Description

The CY7C13451G is a 128 K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).